module Alu (op,a,b,zero,result);
    input [3:0] op;
    input [31:0] a,b;
    output zero;
    output reg[31:0] result;
    parameter   AND_ALU = 4'b0000, OR_ALU = 4'b0001, ADD_ALU = 4'b0010, SUB_ALU = 4'b0011, SLT_ALU = 4'b0100, XOR_ALU = 4'b0101, LUI_ALU = 4'b0110;
    assign  zero = (result == 32'b0);
    always @(op or a or b) begin
        case(op)
        AND_ALU: result = a & b;
        OR_ALU: result = a | b;
        ADD_ALU: result = a + b;
        SUB_ALU: result = a - b;
        SLT_ALU: result = (a<b)?1:0;
        XOR_ALU: result = a^b;
        LUI_ALU: result = {b[15:0],16'b0000000000000000};
        endcase
    end
endmodule //alu